Study of the operation speed of half-micron design rule CMOS ring oscillators

The operation speed of a 73-stage CMOS ring oscillator with 0.5 μm channel lengths has been investigated. By employing a capacitance-reduced structure, gate delays of 47.4 ps and 49.3 ps with and without substrate bias at room temperature, and of 43.0 ps at 77 K, respectively, have been experimentally obtained at a supply voltage of 5 V. From the evaluation of parasitic capacitances, the speed which is achievable by the proper scaling of the device parameters at a half-micron design rule is estimated to be approximately 30 ps