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A testability strategy for microprocessor architecture

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4 Author(s)
Catthoor, F. ; IMEC, Leuven, Belgium ; van Sas, J. ; Inze, L. ; De Man, H.

The authors present a method for fully testing chips designed using synthesis and silicon compilation. The method is targeted for a multiprocessor architecture that implements low-speed to medium-speed signal-processing algorithms. By taking advantage of the specific properties of the architecture, the method allows a chip to be partitioned into several functional units. The authors use the C-test concept instead of the traditional automatic test-pattern generation to derive a compact set of test vectors. The fault model covers both the stuck-at class and part of the transistor stuck-open and stuck-closed cases. For large units with embedded memory, the authors adopt a self-test approach.<>

Published in:

Design & Test of Computers, IEEE  (Volume:6 ,  Issue: 2 )