Referenced Items are not available for this document.
Drivers, comparators, active loads, and per-pin timing circuitry for a VLSI test system are placed in two CMOS integrated circuits. This level of integration allows fast, low-capacitance pin electronics to be manufactured at relatively low cost. Novel design and calibration techniques are used to overcome limitations of CMOS technology
Published in:
Industrial Electronics, IEEE Transactions on
(Volume:36
,
Issue:
2
)
Date of Publication: May 1989
- Page(s):
- 185 - 191
- ISSN :
- 0278-0046
- INSPEC Accession Number:
- 3408001
- Digital Object Identifier :
- 10.1109/41.19067
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- May 1989
- Sponsored by :
- IEEE Industrial Electronics Society
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