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Calculating the effective pattern rate for high-speed board test applications

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1 Author(s)
Arena, J.J. ; Teradyne Inc., Boston, MA, USA

A complex interplay of tester specifications can force in-circuit and functional board test systems to operate at less than their specified maximum pattern rates in real-world test applications. The author explores the factors that combine to limit test speed. He develops models for calculating the effective pattern rate based on tester performance data and the characteristics of the VLSI board under test

Published in:

Industrial Electronics, IEEE Transactions on  (Volume:36 ,  Issue: 2 )