An approach to the design of VLSI architectures for digital filters using bit level systolic arrays

Describes the design of hardware architectures of wave digital filters (WDF) using bit-level systolic arrays that are suitable for integration. It provides an account of the way in which the arrays are multiplexed and how they may be fully utilised. Unit element and lattice filters are described for a specific design example and VLSI implementation parameter estimates are given.<
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