By Topic

High performance data acquisition systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
McManus, I.D. ; Analog Devices Marketing Ltd., Walton-on-Thames, UK

The author describes the specific considerations which apply in respect of achieving a viable architecture for enabling the proper acquisition of data with frequency components in excess of 100 KHz, using hardware designed to interface with the PC bus. Allied to the above are issues relating to aspects of triggering techniques aimed at maximising the capture of relevant data, and thereby minimising the need for complex data reduction algorithms operating on an excess of raw data. The theme is developed to describe means of acquiring data in an essentially simultaneous manner from multiple channels. Ways are described in which a large subset of the above techniques and circuitry is applied to another form of high performance data acquisition, in this case characterised by high (16-bit) resolution at still moderately high speed (50-KHz)

Published in:

PC-Based Instrumentation, IEE Colloquium on

Date of Conference:

31 Jan 1990