Fast parallel algorithm for all-pairs shortest path problem and its VLSI implementation

Present a new parallel algorithm to solve the all-pairs shortest path problem in a given graph which is considerably faster than the most recently published algorithm (B.P. Sinha et al. IEEE Trans. Comput. vol.C-35, no.11, p.1000-4, 1986) for the same problem. Next the authors propose a suitable VLSI systolic architecture to map the algorithm and evaluate the performance of the proposed architecture in terms of execution time and interprocessor communication time. They show that the implementation has O(log/sup 2/ n) execution time (compare-exchange time) and O(n log n) communication time compared to O(n log n) and O(n/sup 2/) in B.P. Sinha et al.'s implementation.<>