Forward error correction for BISDN: implementation and analysis

The authors study the implementation and the performance of forward error correction (FEC) schemes for both the asynchronous transfer mode (ATM) header and the adaptation layer. Both serial and parallel implementations are studied. The focus is on the adaptation layer due to the modification needed to accommodate the effect of the self-synchronous scrambler. The analysis includes the computation and approximation of the detection of random and burst errors. From the results of the analysis, it is observed that in the case of burst errors in the adaptation layer, the use of the generator polynomial with the factor (1+x) does not perform as well as a tenth-order primitive polynomial.<
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