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A case study of two-stage fault location

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3 Author(s)
Ryan, P. ; Intel Corp., Folsom, CA, USA ; Davis, K. ; Rawat, S.

An industrial implementation of two-stage VLSI fault location is presented. Two-stage fault location was developed to address the size and computation time problems that were making it impractical to automate fault location with fault dictionaries. It does this by reducing the fault list and the test vector set for each faulty chip before dynamically creating a new, small fault dictionary for each diagnosis. The modern fault dictionary and the two-stage fault location technique are explained. For the case study presented, a new Intel chip was chosen. Its test set was developed and fault simulated, and it was prepared for automated fault location. Two-stage fault location was then applied to the fourteen failures available from initial product development production runs. The results are presented.<>

Published in:

Reliability Physics Symposium 1992. 30th Annual Proceedings., International

Date of Conference:

March 31 1992-April 2 1992

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