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Parallel hardware algorithms with redundant number representations for multiple-valued arithmetic VLSI

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4 Author(s)
Kawahito, S. ; Dept. of Electr. & Electron. Eng., Toyohashi Univ. of Technol., Japan ; Mitsui, Y. ; Ishida, M. ; Nakamura, T.

High-speed arithmetic algorithms based on redundant number representations with the digit set {0,1,2} in radix 2 are presented. The algorithms are suitable for implementing high-speed compact arithmetic in VLSI with multivalued logic circuits. Addition and subtraction can be performed in a constant time independent of the operand length. Internal n-digit multiplication and division using the redundant number representations can be performed in a time proportional to log2 n and n, respectively. The circuits offer higher speed and greater compactness compared with the signed-digit arithmetic, since the basic addition cell has simpler scheme. The addition cell also has sufficient immunity to the supply voltage fluctuation and relatively low power dissipation

Published in:

Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on

Date of Conference:

27-29 May 1992