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Design of a multiple-valued rule-programmable matching VLSI chip for real-time rule-based systems

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3 Author(s)
Hanyu, T. ; Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan ; Takeda, K. ; Higuchi, T.

A multivalued VLSI processor design for fully parallel pattern matching is presented. It can be applied to real-time rule-based systems with large knowledge bases which are programmable. One-digit pattern matching based on direct multivalued encoding of each attribute can be described by only a programmable delta literal. Moreover, the literal circuit can be easily implemented using two floating-gate MOS devices whose threshold voltages are controllable. The inference time of an eight-valued matching processor with 256 rules and conflict resolution circuits is estimated at about 360 ns, and the chip area is reduced to about 10% of that of the equivalent binary implementation

Published in:

Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on

Date of Conference:

27-29 May 1992