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RamLink: a high-bandwidth point-to-point memory architecture

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3 Author(s)
Gjessing, S. ; Oslo Univ., Norway ; Stone, G. ; Wiggers, H.

The authors describe RamLink, a memory interface architecture that allows RAM chips to be connected with point-to-point links in a ring topology. Low-voltage differential driver technology allows for very high throughput: 500 Mbytes/s on an 8-b-parallel data path. A RamLink memory subsystem consists of a memory controller and one or more (maximum 64) RamLink memory chips. A few RamLink chips, built from a conventional DRAM (dynamic RAM) process, provide a simple high-bandwidth memory subsystem. Preliminary simulations verify that the RamLink architecture has a very high system bandwidth with latency comparable to that of conventional memory systems. RamLink is inspired by the IEEE Scalable Coherent Interface specification (P1596) and has been authorized as an IEEE working group (P1596.4).<>

Published in:

Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.

Date of Conference:

24-28 Feb. 1992