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DFT standards allow optimized tester configuration to reduce cost of test

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2 Author(s)
V. P. LaBuda ; Motorola Inc., Scottsdale, AZ, USA ; R. Youngblood

High-pin-count testers for silicon employing design-for-testability (DFT) techniques are examined as they relate to facilitating low-cost test of application-specific integrated circuits (ASICs). One test methodology takes advantage of DFT schemes emerging in silicon to provide inexpensive testing. Implementation of DFT as part of this low-cost test approach is presented, along with the resulting DFT versus tester flexibility tradeoffs. An evaluation of this synergy is given by looking at how key issues (e.g. test speed, silicon overhead, etc.) facing both designer and test vendor are handled

Published in:

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Date of Conference:

17-21 Sep 1990