By Topic

Quick estimation of transient currents in CMOS integrated circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Martinez, A.M. ; VLSI Technol. Inc., Santa Clara, CA, USA

A methodology is established for analyzing transient currents in CMOS VLSI circuits without extensive detailed circuit simulations. Equations are presented for the analyzing individual device currents using transistor dimensions, rise/fall times, frequency, and capacitive loading. The concept of effective frequency for various transistor structures is introduced and used for frequency propagation in complex circuits. Simple algorithms are presented for differentiating between simultaneous and nonsimultaneous currents using frequency, propagation delay, and power-bus location. Current flow is analyzed in general for three structures: interconnect, internal power buses, and pad-ring power buses. Individual transistor currents are related to total current in VLSI circuits. Current values and percentage errors are given to various examples. These current estimates can flag serious reliability issues, such as electromigration, or spurious signal noise from excessive power-bus voltage drops

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 2 )