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Reliability, testability and yield of majority voting VLSI

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2 Author(s)
Stroud, C.E. ; AT&T Bell Lab., Naperville, IL, USA ; Barbour, A.E.

Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved

Published in:

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Date of Conference:

17-21 Sep 1990