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SPIM: a pipelined 64*64-bit iterative multiplier

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2 Author(s)
M. R. Santoro ; Center for Integrated Syst., Stanford Univ., CA, USA ; M. A. Horowitz

A 64*64-bit iterating multiplier, the Stanford pipelined iterative multiplier (SPIM), is presented. The pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a partial array to be used, which reduces area. SPIM was fabricated in a 1.6- mu m CMOS process. It has a core size of 3.8 mm*6.5 mm and contains 41000 transistors. The on-chip clock generator runs at an internal clock frequency of 85 MHz. The latency for a 64*64-bit fractional multiply is under 120 ns, with a pipeline rate of one multiply every 47 ns.<>

Published in:

IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 2 )