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Efficient timing analysis for general synchronous and asynchronous circuits

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3 Author(s)
Yuan-Hua Chu ; Electron. Res. & Service Organ., Hsinchu, Taiwan ; Yih-June Liou ; Jong-Leih Chen

After partitioning the circuit into a set of clock groups, an event-driven approach is used to find paths with delays greater than a given threshold value. False paths detected during event propagation are reported to the user. In addition to breaking asynchronous loops dynamically, the tool also checks setup/hold time and minimum pulse width violations in a multiple clock environment. Experimental results are shown to demonstrated the efficiency and effectiveness of the proposed algorithms

Published in:
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Date of Conference: 17-21 Sep 1990

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