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ASIC design in a next generation workstation

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1 Author(s)
Young, M.S. ; Sun Microsystems Inc., Mountain View, CA, USA

The activities of the design team formed for development of a follow-on machine to the Sparcstation 1 are discussed. The design team partitioned the design into four chips: the cache controller (CACHE+), memory management unit (MMU+), direct memory access (DMA+), and dynamic memory controller (RAM+). Architectural changes and higher integration eliminated two of the ASICs used on the Sparcstation 1 and dropped the usage of one of the ASICs from two to one part per board. One ASIC, a video controller, was reused. The manpower requirements of the project and the design/verification tools used by the design team are discussed

Published in:

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Date of Conference:

17-21 Sep 1990