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RELIANT: a reliability analysis tool for VLSI interconnect

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2 Author(s)
D. F. Frost ; Dept. of Electr. & Electron. Eng., Stellengbosch Univ., South Africa ; K. F. Poole

RELIANT, as a CAD (computer-aided design) tool that predicts the failure rate of integrated circuit conductors, is presented. A circuit layout, device models, and process-dependent reliability data are inputs to RELIANT. The interconnect patterns, in a Caltech Intermediate Format (CIF) mask description file, are fractured into a number of characteristic segment types. An equivalent circuit for the interconnect topology is extracted and used in conjunction with SPICE to determine the transient currents in each segment. Using parametric models for electromigration damage, the failure rate of the system is computed, as a function of time. The reliability models are calibrated using lifetime measurements performed on a set of conductor test structures. RELIANT provides designers with feedback on the reliability hazards of a design. Results show the application of the tool to a standard-cell CMOS component. For modeling large VLSI interconnect systems, the incorporation of a switched-level simulator for determining approximate current waveforms is discussed.<>

Published in:

IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 2 )