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An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application

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8 Author(s)
Furuyama, T. ; Toshiba Corp., Kawasaki, Japan ; Ohsawa, T. ; Nagahama, Y. ; Tanaka, H.
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A multiple-level 2-bit/cell storage technique for DRAMs (dynamic random-access memories) has been developed. The total RAM area is reduced and the cell array is cut in half. Since the memory cell area is especially defect-sensitive, this technique is highly effective for process yield improvement. Reasonable access time has been realized with this technique: 170 ns is still fast enough for many ASIC (application-specific integrated circuit) memory applications. This technique meets the requirement of high density and moderate speed. It was found that the 2-bit/cell storage technique is suitable for macrocell or memory-on-logic type application.<>

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 2 )

Date of Publication:

April 1989

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