By Topic

Automatic test chip and test program generation: an approach to parametric test computer-aided design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

For each new CMOS technology, the design of the associated test chip and test program requires much effort. To reduce this design cycle the authors have developed an integrated test chip and test program generation system, which generates automatically and concurrently all the tools necessary for parametric data acquisition, and optimizes the test structure design according to the foreseen electrical characteristics. The authors have defined standard design rules that are independent of any technology using the method of the mnemonics. The goal was to speed up the generation of a test chip, allowing the development and stabilization of double-metal double-polysilicon CMOS technologies. A test chip layout generator, MODULE, and a test program generator, PARAM, were developed. With both these generators it is possible, for a given CMOS technology described by its design and electrical rule packages, to generate automatically and concurrently the test structures, modules, and programs necessary for parametric data acquisition

Published in:

Microelectronic Test Structures, 1992. ICMTS 1992. Proceedings of the 1992 International Conference on

Date of Conference:

16-19 Mar 1992