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A dynamic programming processor for speech recognition

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4 Author(s)
Quenot, G.M. ; LIMSI-CNRS, Orsay, France ; Gauvain, J. ; Gangolf, J.-J. ; Mariani, J.J.

A dynamic programming processor with parallel and pipeline architecture is described. A 2- mu m CMOS technology was applied to the DP processor, which is composed of 127309 transistors on a 7.17*8.62-mm/sup 2/ die and is housed in an 84-pin PLCC (plastic leaded chip carrier) or PGA (pin grid array) package. The clock frequency is 20 MHz, and the instruction cycle time is 100 ns. Precise electrical simulations permitted the safe use of nonstandard logic and area and power reduction. Implementation of a direct access to all internal registers has proven useful for chip test and software development. A system using one DP processor has given very good results on a wide variety of applications and 0.48% error rate on tests with standard NATO tapes. These results are significantly better than those published for other systems on the same tests.<>

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Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 2 )