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An analog PLL-based clock and data recovery circuit with high input jitter tolerance

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1 Author(s)
Sun, S.Y. ; Rockwell Int., Newport Beach, CA, USA

A clock and data recovery circuit for a T1 network is described. A fully integrated phase-locked loop (PLL) extracts the carrier signal embedded in the data. Two trimming DACs simultaneously bring the VCO center frequency and the PLL closed-loop bandwidth to their specified values. A triple sampler captures the jittering data and aligns them with the recovered clock. The input jitter of this circuit is three times more than previously reported PLL-based circuits

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 2 )