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A programmable analog neural network chip

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3 Author(s)
Schwartz, D.B. ; AT&T Bell Lab., Holmdel, NJ, USA ; Howard, R.E. ; Hubbard, W.E.

A generic chip is implemented in CMOS to facilitate studying networks by building them in analog VLSI. By utilizing the well-known properties of charge storage and charge injection in a novel way, the authors have achieved a high enough level of complexity (>10/sup 3/ weights and 10 bits of analog depth) to be interesting, in spite of the limitation of a modest 6.00*3.5-mm/sup 2/ die size required by a multiproject fabrication run. If the cell were optimized to represent fixed-weight networks by eliminating weight decay and bidirectional weight changes, the density could easily be increased by a factor of 2 with no loss in resolution. Once a weight change vector has been written to the RAM cells, charge transfers can be clocked at a rate of 2 MHz, corresponding to peak learning rates of 2*10/sup 9/ weight changes/second and exceeding the throughput of 'neural network accelerators' by two orders of magnitude.<>

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 2 )