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Improved logic synthesis algorithms for table look up architectures

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4 Author(s)
R. Murgai ; Dept. of EECS, California Univ., Berkeley, CA, USA ; N. Shenoy ; R. K. Brayton ; A. Sangiovanni-Vincentelli

The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches.<>

Published in:

Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on

Date of Conference:

11-14 Nov. 1991