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A switch-level matrix approach to transistor-level fault simulation

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2 Author(s)
Lee, T. ; Illinois Univ., Urbana, IL, USA ; Hajj, I.N.

The authors describe a method for performing transistor-level logical fault simulation. The method relies on switch-level modeling and uses a switch-level matrix-equation formulation and solution into which fault models are inserted in a straightforward manner. The fault models include transistor stuck-at, node stuck-at, and bridging faults. Both output voltage monitoring and current testing are used for fault detection. The approach has been implemented in a concurrent fault simulator and tested using both combinational and sequential circuit benchmarks. The results of the simulator compare very favourably with existing switch-level fault simulators while allowing more complete transistor-level fault models to be included.<>

Published in:

Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on

Date of Conference:

11-14 Nov. 1991

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