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Test generation for synchronous sequential circuits based on fault extraction

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2 Author(s)
Pomeranz, I. ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Reddy, S.M.

The authors describe an efficient procedure for translating stuck-at faults in a gate level implementation into state-table faults in a state-table description of the circuit. Based on this fault procedure, a test generation approach is presented for stuck-at faults, which results in short test sequences and achieves complete coverage of stuck-at faults. Experimental results are given for both MCNC and ISCAS-89 benchmark circuits, to demonstrate the applicability of the method.<>

Published in:

Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on

Date of Conference:

11-14 Nov. 1991