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A Monte Carlo simulation environment for wear out in VLSI systems

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3 Author(s)
G. S. Choi ; Coordinated Sci. Lab., Illinois Univ., Urbana-Champaign, IL, USA ; R. K. Iyer ; J. H. Patel

The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switching activity is collected. This data is then used along with Monte Carlo simulation to model wear-out at the chip-level

Published in:

VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on

Date of Conference:

4-8 Jan 1991