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Redundancy removal for sequential circuits without reset states

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1 Author(s)
Kwang-Ting Cheng ; AT&T Bell Labs., Murray Hill, NJ, USA

Methods for identifying and removing redundancy in synchronous sequential circuits that do not have a global reset state are proposed. All existing structure-level test generators use three-valued logic, which is not completely accurate, to process circuits that have an unknown initial state. A fault that is reported undetectable by such test generators is not necessarily redundant. It is shown that if a fault is potentially undetectable (p-undetectable), it is redundant. An algorithm that identifies p-undetectable faults is described. For large circuits, a practical procedure for removing redundancy in the feedback-free portion of the circuits is given. An alternative approach to identifying redundancy that does not require determining the potential detectability of faults is also presented. Derivations of conditions in which undetectable faults are redundant are provided. Algorithms for identifying unactivatable and unpropagable faults are described. These algorithms are implemented and incorporated in the redundancy removal system MIRACLE

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 1 )