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Experimental evaluation of multilevel caches for shared memory multiprocessors

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2 Author(s)
A. Choudhary ; Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA ; S. Krishnamoorthy

Memory subsystem design has become a critical problem in multiprocessor systems. As processor speeds increase, supplying data and instructions at those speeds is crucial in order to obtain any significant performance gains from parallel processing. Multilevel caches have been proposed for multiprocessor systems to reduce traffic on interconnections and main memory. The paper presents experimental results for various cache configurations for two-level caches for multiprocessors. The experimental evaluation is performed by detailed simulations using address traces generated by perfect club benchmark programs as well as other numerical programs executed on multiprocessors. The performance results capture the effects of block size, cache size, ratio of secondary and primary cache size, and, write-through and write-back protocols on hit ratios, access times, relative speedups and bus utilizations. Furthermore, performance of various organizations are studied for both vector and scalar data

Published in:

System Sciences, 1991. Proceedings of the Twenty-Fourth Annual Hawaii International Conference on  (Volume:i )

Date of Conference:

8-11 Jan 1991