Reducing message latency by making message passing transparent

The authors describe hardware to reduce message latency and hide message passing's existence on distributed memory multiprocessors. Existing message passing systems are visible to the programmer and require setup time for each message. The authors propose a system in which normal processor memory reads and writes cause a communications processor to send or receive messages as necessary to implement the read or write operation. To implement this a section of memory is typed, describing the actions needed when that memory is read or written. Communications processor setup commands provide tables giving the memory layout. This can include full/empty bit synchronization, counted writers synchronization, multiple recipients, broadcasting, and remote procedure call support. The authors provide a justification, a mechanism description, and a proposed hardware and software implementation outline