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A systematic approach to bit recursive systolic array design

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2 Author(s)
K. R. Liu ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; K. Yao

This approach provides a systematic way to design a recursive computational architecture instead of a bit-slice architecture. Since the relationship is much stronger at the bit level than at the work level and most relations can be described as shift-and-operate computations, these kinds of relations can be formulated as recursive equations, from which the systolic array can be built without deriving the dependence graph of the bit-level computation. Some design examples for bit-recursive systolic array presented: multiplier, inner product and convolution correlation.<>

Published in:

Systolic Arrays, 1988., Proceedings of the International Conference on

Date of Conference:

25-27 May 1988