By Topic

The design of a systolic array system for linear state equations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shyh-Jye Jou, ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chein-Wei Jen, ; Wen-Zen Shen,

The dependence-graph (DG) approach is extended and applied to the systematic design of a systolic array system. Two DGs that represent two different but data-dependent process algorithms are first linked together. Tag bits are added onto index nodes in this linked DG and used to indicate the different functions to be executed on single processor element. By applying the conventional time-scheduling and node-assignment procedures to this tagged DG, the interfacing communication problem of a systolic array system can be solved and the optimal latency can be easily obtained. Using this method, an optimal linear-state solver has been designed.<>

Published in:

Systolic Arrays, 1988., Proceedings of the International Conference on

Date of Conference:

25-27 May 1988