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Validatable nonrobust delay-fault testable circuits via logic synthesis

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2 Author(s)
S. Devadas ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; K. Keutzer

The authors advocate a synthesis approach to delay-fault testing, wherein completely path-delay-fault testable circuits are automatically synthesized, meeting area and performance requirements. They give necessary and sufficient conditions for validatable nonrobust fault testability of paths in arbitrary multilevel networks. Validatable nonrobust testing as opposed to robust testing offers degrees of freedom that enable the development of efficient synthesis procedures that target delay-fault testability, and also provides a means of producing compact test vector sets. The authors then focus on the development of synthesis procedures that produce networks that are fully testable under the nonrobust fault model. They show that primality and irredundancy are both a necessary and sufficient condition for complete validatable nonrobust testability in the two-level case. They prove that synthesizing a multilevel network using algebraic factorization retains complete validatable nonrobust testability. Preliminary results that verify the procedures are reported

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:11 ,  Issue: 12 )