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Verified functions for generating signed-binary arithmetic hardware

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1 Author(s)
Shiu-Kai Chin ; Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA

Formally verified metafunctions which synthesize array multipliers and inner product hardware of arbitrary size and structure are presented. The metafunctions operate on signed-binary inputs in general and two's-complement in particular, and are higher order. They are shown to be equivalence-preserving transformations and correctly produce multipliers and inner product hardware of arbitrary size and structure. All the metafunctions, their associated correctness theorems, and their correctness proofs are machine executable within the higher order logic (HOL) theorem prover. The function expressions produced by the metafunctions can be used as hardware synthesis descriptions or as comparison functions for Boolean-comparison-based systems. In addition to the definitions written in higher-order logic, the major definitions are written in a more informal functional programming language-like notation which should facilitate translation of the synthesis functions to other hardware description languages

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 12 )