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Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronic devices

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2 Author(s)
Goodson, K.E. ; Dept. of Mech. Eng., MIT, Cambridge, MA, USA ; Flik, M.I.

Silicon-on-insulator (SOI) electronic circuits have a buried silicon dioxide layer which inhibits device cooling and reduces the thermal packing limit, the largest number of devices per unit substrate area for which the device operating temperature is acceptably low. Thermal analysis yields the packing limit of SOI MOSFET devices in terms of the targeted channel-to-substrate thermal conductance. Thermal conduction is microscale if it is significantly reduced by the boundary scattering of heat carriers, phonons in silicon and electrons in aluminum. Microscale effects are negligible above room temperature, but may reduce the packing limit by 44% for a substrate temperature of 77 K

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Components, Hybrids, and Manufacturing Technology, IEEE Transactions on  (Volume:15 ,  Issue: 5 )