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An optimum parallel architecture for high-speed real-time digital signal processing

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6 Author(s)
G. R. Lang ; Motorola Inf. Syst., Brampton, Ont., Canada ; M. Dharssi ; F. M. Longstaff ; P. S. Longstaff
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The authors describe a parallel processing architecture for real-time digital signal processing that has demonstrated virtually 100% data processing efficiency in a number of areas. The Teamed-Architecture Signal Processor (T-ASP) is a field-proven, commercially available optimal system solution to the extremely high computational and I/O rates encountered in modern digital-signal-processing environments. The design of T-ASP involves the consideration and implementation of many architectural concepts used to enhance the performance of a computer, including programmability, parallel processing, vector processing and pipelining, memory interleaving, double cache memories, multiple high-speed I/O interfaces, and segmentation of the processors for elimination of both CPU and data-handling overhead. The authors discuss hardware architecture design and implementation; hardware management; and software architecture design and implementation.<>

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Computer  (Volume:21 ,  Issue: 2 )