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A versatile dual-mode transposition latch array design for DCT in HDTV applications

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4 Author(s)
Dejhan, K. ; Fac. of Eng., King Mongkut''s Inst. of Technol. Ladkrabang, Bangkok, Thailand ; Cheevasuvit, F. ; Trisuwannawat, T. ; Kaneko, M.

A latch-based dual-mode matrix transposer memory for discrete cosine transform (DCT) data format conversion in HDTV applications is described. 1.2-μm double-metal HCMOS3 technology is used. The static latch cell is 19.7 μm×24.5 μm excluding a pass-transistor multiplexer. By using this technology, the DCT runs at a rate up to 27 megapixels per second. The dimension of the matrix depends on the number of memory points. The memory cell uses the static shift latch with minimum area and power dissipation

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:38 ,  Issue: 4 )

Date of Publication:

Nov 1992

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