Referenced Items are not available for this document.
Built-in current testing is known to enhance the defect coverage in CMOS VLSI. An experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μm p-well CMOS technology. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some implanted open-circuit defects at a clock speed of 30 MHz (limited by the test setup). SPICE3 simulations indicate a defect detection time of about 2 ns
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:28
,
Issue:
1
)
Date of Publication: Jan 1993
- Page(s):
- 72 - 77
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 4360382
- Digital Object Identifier :
- 10.1109/4.179205
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Jan 1993
- Sponsored by :
- IEEE Solid-State Circuits Society
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