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Analysis of logarithmic number system processors

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2 Author(s)
T. Stouraitis ; Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA ; F. J. Taylor

An analysis of a logarithmic number system (LNS) processor is presented. The analysis includes processor designs that overcome the historical limitation of the word-length of LNS, thus increasing the precision of the processor. A 20-bit LNS VLSI chip layout and timing estimates have been produced in cooperation with Honeywell Inc. Using an enhanced 1.25-ns technology, and inserting pipelining registers in the addition/subtraction data path, a 24-bit adaptive radix processor (ARP)/LNS processor can be realized. The predicted performance of the device would be on the order of 20 ns for multiplication/division and 40 ns for addition/subtraction. This class of processors is now supported with a predictive error model. The theoretical studies were supported and verified by computer simulation experiments at all levels of analysis

Published in:

IEEE Transactions on Circuits and Systems  (Volume:35 ,  Issue: 5 )