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Design and analysis of a generalized architecture for reconfigurable m-ary tree structures

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2 Author(s)
S. Srinivas ; Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India ; N. N. Biswas

A generalized architecture is presented for reconfigurable m -ary tree structures, where m is any integer >1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors previously (1990) for obtaining reconfigurable binary tree structures. The generalized architecture with mk processing elements or nodes (where k is any integer >1) is implemented with a k-stage MIN. A single control code issued to the MIN establishes a distinct m-ary tree configuration among the nodes. The favorable features of the architecture include fast reconfiguration, simplified hardware in the nodes and the MIN, and simple routing control. The reconfigurability of the architecture is proved, and the results of the analysis are utilized to provide a procedure to synthesize the m-ary tree configuration that is generated for any given control code. Considerations for implementing the switching elements of the MIN are discussed

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IEEE Transactions on Computers  (Volume:41 ,  Issue: 11 )