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A new low overhead design for testability of programmable logic arrays

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2 Author(s)
Liu, B.D. ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Sheu, J.J.

A new design to reduce the overhead required for fully testable programmable logic arrays (PLAs) is proposed. This design exploits the fact that product lines in a PLA can be rearranged and grouped into few partitions. Then, some extra outputs are added, one per partition, to make the whole PLA testable. Compared with the previous PLA design-for-testability techniques, the algorithm presented is very feasible, and its implementation is straightforward. Furthermore, this algorithm significantly lowers overhead and provides substantially higher fault coverage than some existing schemes

Published in:

Circuits and Systems, 1991., IEEE International Sympoisum on

Date of Conference:

11-14 Jun 1991