Signed multiple-valued PLAs and the design of fast multiple-valued arithmetic operation units for systolic MV-DTW processor

Three new types of multiple-valued programmable logic arrays (MVPLAs) are proposed. Type 1 MVPLA consists of signed literal generators, a MIN array, and MAX arrays. Type 2 MVPLA consists of signed literal generators, an AND array and an OR array, and signed output encoders. Type 3 MVPLA is a two-level PLA which combines the type 2 MVPLA with a two-valued PLA with signed two-bit decoders. The principle of fast multiple-valued arithmetic operation units (addition, absolute value subtraction, and minimization) are presented, and their design is also discussed.<
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