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Power supply ripple reduction techniques for switched-capacitor circuits

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3 Author(s)
B. W. Lee ; Samsung Electronics Co., KyungGi-Do, South Korea ; Y. S. Bae ; S. Y. Baek

In mixed-mode MOS VLSI circuits switching noises generated in digital circuits are inevitably coupled into analog circuits through commonly shared power lines and substrate layer. Three design techniques to reduce the power ripple coupling, which include optimizing individual SC integrators, minimizing input transistor area and applying a stable bias potential, are described. Experimental results using the optimizing technique show more than 8-dB ripple reduction in a switched-capacitor circuit

Published in:

Circuits and Systems, 1991., IEEE International Sympoisum on

Date of Conference:

11-14 Jun 1991