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Systolic multiple-output multipliers for digital signal processing and computer vision

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2 Author(s)
da Fontoura Costa, L. ; Dept. of Electron. & Electr. Eng., London Univ., UK ; Sandler, Mark B.

Word-level, bit-serial and bit-level designs for multiplier-less systolic multiple-output multipliers are described. They are characterized in terms of execution speed, hardware requirement and propagation of signals. Their applications to digital signal processing and computer vision are discussed and exemplified respectively by digital filters and a Hough transform

Published in:

Circuits and Systems, 1991., IEEE International Sympoisum on

Date of Conference:

11-14 Jun 1991