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Uniform design of parallel programs for DSP

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2 Author(s)
Teich, J. ; Inst. of Microelectron., Univ., of Saarland, Saarbrucken, Germany ; Thiele, L.

It is shown that there is a close relationship between the mappings of sequentially formulated algorithms onto different kinds of parallel architectures. The compilation of programs for these architectures shares common optimization features, such as a high degree of parallelism, a short execution time, and a high processor utilization, and also a common design trajectory. Given a problem formulation, parallelism is extracted. Equivalence transformations are applied for the purpose of optimization. In the mapping phase, resources are assigned to operations and a schedule is defined. In order to match a problem and an architecture of given size, hierarchical transformations are performed that partition a problem into problems of smaller size that are executed sequentially. Due to these similarities, design methods known for the design and optimization of processor arrays can be used to solve problems known from the design of vectorizing compilers for supercomputers and vice versa. For defining the tasks of a versatile compiler for massive parallel architectures (COMPAR) a set of parameterized tools is defined that allows the uniformization of the mapping of sequential code onto parameterized parallel architectures

Published in:

Circuits and Systems, 1991., IEEE International Sympoisum on

Date of Conference:

11-14 Jun 1991

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