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The design of multiplierless digital data transmission filters with powers-of-two coefficients

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1 Author(s)
Samueli, H. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA

An efficient search technique is presented for the design of FIR (finite impulse response) digital transmit and receive matched filters whose coefficients are represented by sums and/or differences of powers-of-two. These filters are ideally suited for custom VLSI implementation since power-of-two multipliers are obtained for free in a dedicated hardware implementation. Thus only a few adders or subtracters are required for each tap of the filter, and therefore fairly high-order filters can be implemented on a single VLSI chip. Due to their very simple structure these multiplierless filters could potentially operate at very high sampling rates to accommodate baud rates in the microwave digital radio range

Published in:

Telecommunications Symposium, 1990. ITS '90 Symposium Record., SBT/IEEE International

Date of Conference:

3-6 Sep 1990