A 7 K gate self-testable scalar-product processor for high definition video transmission applications

A 7000-gate VLSI GaAs chip using a very low power E-D logic family is described. The chip is custom designed to perform signal processing operations at 75 Mpixels/s for HDTV signal coordinate transformations. The 9 mm*7.5 mm chip dissipates only 3.1 W, and includes sophisticated on-chip self-test to verify full speed operation of the three 9*9 multipliers and other circuitry. System testing of the chips operation up to 95 Mpixel/s, which is more than 6 times the present processing rates. Only three such generators are needed to implement a full coordinate transformation greatly reducing the part count and cost of achieving real-time 74.25 Mpixel/s systems.<
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