By Topic

Planar embedding: linear-time algorithms for vertex placement and edge orderings

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
R. Jayakumar ; Fac. of Eng. & Comput. Sci., Concordia Univ., Montreal, Que., Canada ; K. Thulasiraman ; M. N. S. Swamy

The problem of obtaining a planar embedding of a biconnected planar graph is discussed. The approach is based on the planarity testing algorithm of A. Lemple, et al. (1966) and its implementation using PQ-trees. In the planar embedding the vertices of the planar graph are placed in the plane at different horizontal and vertical levels so that no two distinct vertices appear in the same horizontal or vertical level, and higher-numbered vertices appear at higher vertical levels. The left-to-right order of the vertices in such a planar embedding is called the vertex order. For each vertex i, the anticlockwise order in which edges enter i from lower numbered neighbors is denoted by τ(i). Linear-time algorithms to determine a τ(i) for each i, and the vertex order, are developed. The vertex order captures the structural information about the relative placement of vertices in a planar embedding provided by the PQ-tree reduction algorithm. A systematic procedure to obtain an intersection-free drawing of the edges is described. A linear-time algorithm to construct a very compact horvert representation of a planar graph is also presented. This algorithm does not require the construction of the dual of the original graph

Published in:

IEEE Transactions on Circuits and Systems  (Volume:35 ,  Issue: 3 )