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Delay-fault diagnosis by critical-path tracing

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3 Author(s)
Girard, P. ; Montpellier II Univ., France ; Landrault, C. ; Pravossoudovitch, S.

A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented.<>

Published in:

Design & Test of Computers, IEEE  (Volume:9 ,  Issue: 4 )

Date of Publication:

Dec. 1992

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